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Q: What is "FinFET" technology, and why did it replace planar MOSFETs at lower nodes?
Ans: As transistors shrank below 20nm, planar MOSFETs suffered from massive "Short Channel Effects" and leakage current. FinFET (Fin Field-Effect Transistor) introduces a 3D "fin" structure that wraps the gate around three sides of the channel. This provides much better electrostatic control, significantly reducing leakage and allowing for further scaling down to 3nm and beyond.
Q: How does Power Gating differ from Clock Gating?
Ans: * Clock Gating reduces dynamic power by shutting off the clock signal to idle registers, preventing unnecessary switching.
Power Gating reduces leakage (static) power by completely shutting off the current supply to a block of the chip when not in use. While more effective at saving power, power gating is more complex as it requires state retention registers and power-up/down sequences.
Q: What is the significance of "Static Timing Analysis" (STA) in the VLSI flow?
Ans: STA is a method of validating the timing performance of a circuit by checking all possible path delays without requiring a dynamic simulation. It is significantly faster than simulation and provides 100% path coverage. It ensures that the design will operate at the intended clock frequency across different "corners" (process, voltage, and temperature variations).
Q: What is Metastability, and how is it mitigated in Multi-Clock Domain (CDC) designs?
Ans: Metastability occurs when a signal is sampled during its transition period (violating setup/hold times), causing the output to hover between logic '0' and '1' for an indeterminate time. In Clock Domain Crossing (CDC), we mitigate this using Synchronizers (typically a chain of two or more Flip-Flops) or Asynchronous FIFOs for data buses, ensuring the signal settles before being used by the destination domain.
Q: Explain the concept of "Setup Time" and "Hold Time" violations.
Ans: * Setup Time: The minimum time before the clock edge that the data must be stable. A violation occurs if the data path is too slow, often solved by reducing combinational logic or increasing clock period.
Hold Time: The minimum time after the clock edge that the data must remain stable. A violation occurs if the data path is too fast, often solved by inserting buffers. Note: Unlike setup violations, hold violations cannot be fixed by lowering the clock frequency; they must be fixed in the silicon layout.
Q: Why is Verilog/SystemVerilog preferred over VHDL in the modern industry?
Ans: While both are powerful Hardware Description Languages (HDLs), SystemVerilog has become the industry standard for verification due to the UVM (Universal Verification Methodology). It offers superior object-oriented programming features, constrained random stimulus, and functional coverage capabilities that VHDL lacks, making it essential for complex SoC (System on Chip) verification.
Q: What is the primary difference between FPGA and ASIC design flows?
Ans:The main difference is flexibility vs. performance. ASICs (Application-Specific Integrated Circuits) are custom-manufactured for a specific task, offering the highest performance, lowest power consumption, and lowest per-unit cost at high volumes, but they cannot be altered after fabrication. FPGAs (Field-Programmable Gate Arrays) are pre-manufactured silicon that can be reprogrammed in the field. While they have higher power consumption and lower speeds compared to ASICs, they offer zero-cost hardware updates and faster time-to-market.